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1 1998 integrated device technology, inc. dsc-3208/3 ? december 1998 cmos dual asynchronous fifo dual 256 x 9, dual 512 x 9, dual 1,024 x 9, dual 2,048 x 9, dual 4,096 x 9, dual 8,192 x 9 idt7280 idt7281 idt7282 idt7283 idt7284 idt7285 features: ? the 7280 is equivalent to two 7200 256 x 9 fifos ? the 7281 is equivalent to two 7201 512 x 9 fifos ? the 7282 is equivalent to two 7202 1,024 x 9 fifos ? the 7283 is equivalent to two 7203 2,048 x 9 fifos ? the 7284 is equivalent to two 7204 4,096 x 9 fifos ? the 7285 is equivalent to two 7205 8,192 x 9 fifos ? low power consumption active: 685 mw (max.) power-down: 83 mw (max.) ? ultra high speed12 ns access time ? asynchronous and simultaneous read and write ? offers optimal combination of data capacity, small foot print and functional flexibility ? ideal for bi-directional, width expansion, depth expansion, bus- matching, and data sorting applications ? status flags: empty, half-full, full ? auto-retransmit capability ? high-performance cmos technology ? space-saving tssop ? industrial temperature range (C40 o c to +85 o c) is available description: the idt7280/7281/7282/7283/7284/7285 are dual-fifo memories that load and empty data on a first-in/first-out basis. these devices are functional and compatible to two 7200/7201/7202/7203/7204/7205 fifos in a single package with all associated control, data, and flag lines assigned to separate pins. the devices use full and empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. the reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. data is toggled in and out of the devices through the use of the write ( w ) and read ( r ) pins. the devices utilize a 9-bit wide data array to allow for control and parity bits at the users option. this feature is especially useful in data commu- nications applications where it is necessary to use a parity bit for transmis- sion/reception error checking. it also features a retransmit ( rt ) capability that allows for reset of the read pointer to its initial position when rt is pulsed low to allow for retransmission from the beginning of data. a half-full flag is available in the single device mode and width expansion modes. these fifos are fabricated using idts high-speed cmos technology. they are designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. functional block diagram wa write control read control ra flag logic expansion logic xia write pointer read pointer data inputs reset logic three- state buffers data outputs rsa fla / rta xoa / hfa ffa efa wb write control read control rb flag logic expansion logic xib write pointer ram array b 256 x 9 512 x 9 1,024 x 9 2,048 x 9 4,096 x 9 8,192 x 9 read pointer data inputs reset logic three- state buffers data outputs rsb flb / rtb 3208 drw 01 xob / hfb ffb efb (da 0 -da 8 ) (db 0 -db 8 ) (qb 0 -qb 8 ) (qa 0 -qa 8 ) ram array a 256 x 9 512 x 9 1,024 x 9 2,048 x 9 4,096 x 9 8,192 x 9
2 idt idt7280/81/82 pin configuration absolute maximum ratings symbol rating com'l & ind'l unit v term terminal voltage with C0.5 to +7.0 v respect to gnd t stg storage temperature C55 to +125 o c i out dc output current C50 to +50 ma note: 3208 tbl 01 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. ac test conditions input pulse levels gnd to 3.0v input rise/fall times 5ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 1 3208 tbl 08 capacitance (t a = +25 o c, f = 1.0 mhz) symbol parameter condition max. unit c in input capacitance v in = 0v 8 pf c out output capacitance v out = 0v 8 pf note: 2679 tbl 02 1. characterized values, not currently tested. symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd supply voltage 0 0 0 v v ih (1) input high voltage 2.0 v v il (2) input low voltage 0.8 v t a operating temperature 0 70 o c commercial t a operating temperature C40 85 o c industrial notes: 3208 tbl 03 1. for rt / rs / xi input, v ih = 2.6v (commercial). 2. 1.5v undershoots are allowed for 10ns once per cycle. recommended dc operating conditions tssop (so56-2, order code: pa) top view ffa qa 0 qa 1 qa 2 qa 3 qa 8 gnd ra qa 4 qa 5 qa 6 qa 7 xoa / hfa efa ffb qb 0 qb 1 qb 2 qb 3 qb 8 gnd rb qb 4 qb 5 qb 6 qb 7 xob / hfb efb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 xia da 0 da 1 da 2 da 3 da 8 wa v cc da 4 da 5 da 6 da 7 fla / rta rsa xib db 0 db 1 db 2 db 3 db 8 wb v cc db 4 db 5 db 6 db 7 flb / rtb rsb 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 3208 drw 02 3208 drw 03 30pf* 1.1k 5v to output pin 680 w or equivalent circuit idt7280l idt7283l idt7281l idt7284l idt7282l idt7285ll com'l & ind'l (1) com'l & ind'l (1) t a = 12, 15, 20 ns t a = 12, 15, 20 ns symbol parameter min. max. min. max. unit i li (2) input leakage current (any input) C1 1 C1 a i lo (3) output leakage current C10 10 C10 10 a v oh output logic 1 voltage i oh = C2ma 2.4 2.4 v v ol output logic 0 voltage i ol = 8ma 0.4 0.4 v i cc1 (4,5) active power supply current (both fifos) 125 (6) 150 ma i cc2 (4,7) standby current ( r = w = rs = fl / rt =v ih ) 15 15ma dc electrical characteristics (commercial: v cc = 5v 10%, t a = 0 o c to +70 o c; industrial: v cc = 5v 10%, t a = C40 o c to +85 o c) notes: 1. industrial temperature range product for the 20ns speed grade is available as a standard device. all other speed grades are available by special order. 2. measurements with 0.4 v in v cc . 3. r 3 v ih , 0.4 v out v cc . 4. tested with outputs open (i out = 0). 5. tested at f = 20 mhz. 6. typical i cc1 = 2*[15 + 2*f s + 0.02*c l *f s ] (in ma) with v cc = 5v, t a = 25 o c, f s = wclk frequency = rclk frequency (in mhz, using ttl levels), data switching at f s /2, c l = capacitive load (in pf). 7. all inputs = v cc - 0.2v or gnd + 0.2v. figure 1. output load * includes scope and jig capacitances.
3 idt idt7280/81/82 ac electrical characteristics (1) (commercial: v cc = 5v 10%, t a = 0 o c to +70 o c; industrial: v cc = 5v 10%, t a = C40 o c to +85 o c) commercial com'l & ind'l (2) 7280l12 7280l15 7280l20 7281l12 7281l15 7281l20 7282l12 7282l15 7282l20 7283l12 7283l15 7283l20 7284l12 7284l15 7284l20 7285l12 7285l15 7285l20 symbol parameter min. max. min. max. min. max. unit t s shift frequency 50 40 33.3 m h z t rc read cycle time 20 25 30 ns t a access time 12 15 20 ns t rr read recovery time 8 10 10 ns t rpw read pulse width (3) 12 15 20 ns t rlz read pulse low to data bus at low z (4) 333ns t wlz write pulse high to data bus at low z (4,5) 555ns t dv data valid from read pulse high 5 5 5 ns t rhz read pulse high to data bus at high z (4) 121515ns t wc write cycle time 20 25 30 ns t wpw write pulse width (3) 12 15 20 ns t wr write recovery time 8 10 10 ns t ds data set-up time 9 11 12 ns t dh data hold time 0 0 0 ns t rsc reset cycle time 20 25 30 ns t rs reset pulse width (3) 12 15 20 ns t rss reset set-up time (4) 12 15 20 ns t rsr reset recovery time 8 10 10 ns t rtc retransmit cycle time 20 25 30 ns t rt retransmit pulse width (3) 12 15 20 ns t rts retransmit set-up time (4) 12 15 20 ns t rtr retransmit recovery time 8 10 10 ns t efl reset to empty flag low 12 25 30 ns t hfh,ffh reset to half-full and full flag high 17 25 30 ns t rtf retransmit low to flags valid 20 25 30 ns t ref read low to empty flag low 12 15 20 ns t rff read high to full flag high 14 15 20 ns t rpe read pulse width after ef high 12 15 20 ns t wef write high to empty flag high 12 15 20 ns t wff write low to full flag low 14 15 20 ns t whf write low to half-full flag low 17 25 30 ns t rhf read high to half-full flag high 17 25 30 ns t wpf write pulse width after ff high 12 15 20 ns t xol read/write to xo low 12 15 20 ns t xoh read/write to xo high 12 15 20 ns t xi xi pulse width (3) 12 15 20 ns t xir xi recovery time 8 10 10 ns t xis xi set-up time 8 10 10 ns notes: 3208 tbl 06 1. timings referenced as in ac test conditions. 2. industrial temperature range is available by special order for speed grades faster than 20ns. 3. pulse widths less than minimum value are not allowed. 4. values guaranteed by design, not currently tested. 5. only applies to read data flow-through mode.
4 idt idt7280/81/82 signal descriptions inputs: data in (d 0 C d 8 ) data inputs for 9-bit wide data. controls: reset ( rs rs rs rs rs ) reset is accomplished whenever the reset ( rs ) input is taken to a low state. during reset, both internal read and write pointers are set to the first location. a reset is required after power up before a write operation can take place. both the read enable ( r r r r r ) and write enable ( w w w w w ) inputs must be in the high state during the window shown in figure 2, (i.e., t rss before the rising edge of rs rs rs rs rs ) and should not change until t rsr after the rising edge of rs rs rs rs rs . half-full flag ( hf hf hf hf hf ) will be reset to high after reset ( rs rs rs rs rs ). write enable ( w w w w w ) a write cycle is initiated on the falling edge of this input if the full flag ( ff ) is not set. data set-up and hold times must be adhered to with respect to the rising edge of the write enable ( w ). data is stored in the ram array sequentially and independently of any on-going read operation. after half of the memory is filled and at the falling edge of the next write operation, the half-full flag ( hf ) will be set to low and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. the half-full flag ( hf ) is then reset by the rising edge of the read operation. to prevent data overflow, the full flag ( ff ) will go low, inhibiting further write operations. upon the completion of a valid read operation, the full flag ( ff ) will go high after t rff , allowing a valid write to begin. when the fifo is full, the internal write pointer is blocked from w , so external changes in w will not affect the fifo when it is full. read enable ( r r r r r ) a read cycle is initiated on the falling edge of the read e nable ( r ) provided the empty flag ( ef ) is not set. the data is accessed on a first-in/first- out basis, independent of any ongoing write operations. after read enable ( r ) goes high, the data outputs (q 0 C q 8 ) will return to a high impedance condition until the next read operation. when all data has been read from the fifo, the empty flag ( ef ) will go low, allowing the final read cycle but inhibiting further read operations with the data outputs remaining in a high impedance state. once a valid write operation has been accomplished, the empty flag ( ef ) will go high after t wef and a valid read can then begin. when the fifo is empty, the internal read pointer is blocked from r so external changes in r will not affect the fifo when it is empty. first load/retransmit ( fl fl fl fl fl / rt rt rt rt rt ) this is a dual-purpose input. in the depth expansion mode, this pin is grounded to indicate that it is the first loaded (see operating modes). in the single device mode, this pin acts as the retransmit input. the single device mode is initiated by grounding the expansion in ( xi ). these devices can be made to retransmit data when the retransmit enable control ( rt ) input is pulsed low. a retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. read enable ( r ) and write enable ( w ) must be in the high state during retransmit. this feature is useful when less than 256/512/1,024/2,048/4,096/ 8,192 writes are performed between resets. the retransmit feature is not compatible with the depth expansion mode and will affect the half-full flag ( hf ), depending on the relative locations of the read and write pointers. expansion in ( xi xi xi xi xi ) this input is a dual-purpose pin. expansion in ( xi ) is grounded to indicate an operation in the single device mode. expansion in ( xi ) is connected to expansion out ( xo ) of the previous device in the depth expansion or daisy chain mode. outputs: full flag ( ff ff ff ff ff ) the full flag ( ff ) will go low, inhibiting further write operation, when the write pointer is one location less than the read pointer, indicating that the device is full. if the read pointer is not moved after reset ( rs ), the full-flag ( ff ) will go low after 256 writes for idt7280, 512 writes for the idt7281, 1,024 writes for the idt7282, 2,048 writes for the idt7283, 4,096 writes for the idt7284 and 8,192 writes for the idt7285. empty flag ( ef ef ef ef ef ) the empty flag ( ef ) will go low, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. expansion out/half-full flag ( xo xo xo xo xo / hf hf hf hf hf ) this is a dual-purpose output. in the single device mode, when expan- sion in ( xi ) is grounded, this output acts as an indication of a half-full memory. after half of the memory is filled and at the falling edge of the next write operation, the half-full flag ( hf ) will be set low and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. the half-full flag ( hf ) is then reset by using rising edge of the read operation. in the depth expansion mode, expansion in ( xi ) is connected to expansion out ( xo ) of the previous device. this output acts as a signal to the next device in the daisy chain by providing a pulse to the next device when the previous device reaches the last location of memory. data outputs (q 0 C q 8 ) data outputs for 9-bit wide data. this data is in a high impedance condition whenever read ( r ) is in a high state.
5 idt idt7280/81/82 figure 4. full flag from last write to first read notes: 1. ef , ff , hf may change status during reset, but flags will be valid at t rsc . 2. w and r = v ih around the rising edge of rs . figure 2. reset figure 3. asynchronous write and read operation w rs r ef hf , ff t rsc t rs t rss t rss t rsr t efl t hfh , t ffh 3208 drw 04 t a r t rc data out valid data out valid t rpw t rlz t dv t a t rhz t rr t wc t wr t wpw data in valid data in valid t ds t dh q 0 -q 8 3208 drw 05 w d 0 -d 8 last write r ignored write first read additional reads first write w ff t wff t rff 3208 drw 06
6 idt idt7280/81/82 figure 5. empty flag from last read to first write figure 8. minimum timing for a full flag coincident write pulse figure 7. minimum timing for an empty flag coincident read pulse figure 6. retransmit last read r ignored read first write additional writes first read w ef t wef 3208 drw 07 valid valid t a data out ref t t rtc t rt t rts rt w , r hf , ef , ff t rtr flag valid 3208 drw 08 rtf t ef w r t wef t rpe 3208 drw 09 ff r w t rff t wpf 3208 drw 10
7 idt idt7280/81/82 figure 9. half-full flag timing figure 10. expansion out figure 11. expansion in operating modes: care must be taken to assure that the appropriate flag is monitored by each system (i.e. ff is monitored on the device where w is used; ef is monitored on the device where r is used). single device mode a single idt7280/7281/7282/7283/7284/7285 may be used when the application requirements are for 256/512/1,024/2,048/4,096/8,192 words or less. these fifos are in a single device configuration when the expansion in ( xi ) control input is grounded (see figure 12). depth expansion these devices can easily be adapted to applications when the require- ments are for greater than 256/512/1,024/2,048/4,096/8,192 words. figure 14 demonstrates a four-fifo depth expansion using two idt7280/7281/ 7282/7283/7284/7285s. any depth can be attained by adding additional idt7280/7281/7282/7283/7284/7285s. these fifos operate in the depth expansion mode when the following conditions are met: 1. the first fifo must be designated by grounding the first load ( fl ) control input. 2. all other fifos must have fl in the high state. 3. the expansion out ( xo ) pin of each device must be tied to the expansion in ( xi ) pin of the next device. see figure 14. 4. external logic is needed to generate a composite full flag ( ff ) and empty flag ( ef ). this requires the oring of all ef s and oring of all ff s (i.e. all must be set to generate the correct composite ff or ef ). see figure 14. 5. the retransmit ( rt ) function and half-full flag ( hf ) are not available in the depth expansion mode. r w hf t rhf 3208 drw 11 half-full or less more than half-full half-full or less t whf r w xo 3208 drw 12 write to last physical location t xol t xoh read from last physical location t xol t xoh w xi r 3208 drw 13 write to first physical location read from first physical location t xis t xir t xi t xis
8 idt idt7280/81/82 figure 13. block diagram of 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18 fifo memory used in width expan sion mode figure 12. block diagram of one 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 fifo used in single device mode usage modes: width expansion word width may be increased simply by connecting the corresponding input control signals of multiple fifos. status flags ( ef , ff and hf ) can be detected from any one fifo. figure 13 demonstrates an 18-bit word width by using the two fifos contained in the idt7280/7281/7282/7283/7284/ 7285s. any word width can be attained by adding fifos (figure 13). bidirectional operation applications which require data buffering between two systems (each system capable of read and write operations) can be achieved by pairing idt7280/7281/7282/7283/7384/7285s as shown in figure 16. both depth expansion and width expansion may be used in this mode. data flow-through two types of flow-through modes are permitted, a read flow-through and write flow-through mode. for the read flow-through mode (figure 17), the fifo permits a reading of a single word after writing one word of data into an empty fifo. the data is enabled on the bus in (t wef + t a ) ns after the rising edge of w , called the first write edge, and it remains on the bus until the r line is raised from low-to-high, after which the bus would go into a three-state mode after t rhz ns. the ef line would have a pulse showing temporary deassertion and then would be asserted. in the write flow-through mode (figure 18), the fifo permits the writing of a single word of data immediately after reading one word of data from a full fifo. the r line causes the ff to be deasserted but the w line being low causes it to be asserted again in anticipation of a new data word. on the rising edge of w , the new word is loaded in the fifo. the w line must be toggled when ff is not asserted to write new data in the fifo and to increment the write pointer. compound expansion the two expansion techniques described above can be applied together in a straightforward manner to achieve large fifo arrays (see figure 15). write ( w ) data in (d) full flag ( ff ) reset ( rs ) 9 read ( r ) 9 data out (q) empty flag ( ef ) retransmit ( rt ) expansion in ( xi ) ( hf ) fifo a or b idt 7280 7281 7282 7283 7284 7285 (half-full flag) 3208 drw 14 xia xib 9 9 18 9 18 hfb hfa 9 data write ( w ) full flag ( ffa ) reset ( rs ) (d) in read ( r ) empty flag ( efb ) retransmit ( rt ) data (q) out 3208 drw 15 fifo a fifo b 7280/7281/7282/ 7283/7284/7285
9 idt idt7280/81/82 figure 14. block diagram of 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 fifo memory (depth expansion) table i?reset and retransmit single device configuration/width expansion mode inputs internal status outputs mode rs rs rs rs rs rt rt rt rt rt xi xi xi xi xi read pointer write pointer ef ef ef ef ef ff ff ff ff ff hf hf hf hf hf reset 0 x 0 location zero location zero 0 1 1 retransmit 1 0 0 location zero unchanged x x x read/write 1 1 0 increment (1) increment (1) xxx note: 2679 tbl 09 1. pointer will increment if flag is high. table ii?reset and first load truth table depth expansion/compound expansion mode inputs internal status outputs mode rs rs rs rs rs fl fl fl fl fl xi xi xi xi xi read pointer write pointer ef ef ef ef ef ff ff ff ff ff reset first device 0 0 (1) location zero location zero 0 1 reset all other devices 0 1 (1) location zero location zero 0 1 read/write 1 x (1) x x x x note: 2679 tbl 10 1. xi is connected to xo of previous device. see figure 14. rs = reset input, fl / rt = first load/retransmit, ef = empty flag output, ff = full flag output, xi = expansion input, hf = half-full flag output d w ffb efb flb xob rsa full empty v cc r 9 9 99 xib 9 q ffa efa fla xoa xia ffb efb flb xib 3208 drw 16 xoa fifo a fifo b fifo a fifo b xia xob efa fla ffa 7280/7281/ 7282/7283/ 7284/7285 7280/7281/ 7282/7283/ 7284/7285
10 idt idt7280/81/82 figure 17. read data flow-through mode figure 16. bidirectional fifo mode notes: 1. for depth expansion block see section on depth expansion and figure 14. 2. for flag detection see section on width expansion and figure 13. figure 15. compound fifo expansion idt7280/7281/ 7282/7283/ 7284/7285 depth expansion block r , w , rs d 0 -d n idt7280/7281/ 7282/7283/ 7284/7285 depth expansion block idt7280/7281/ 7282/7283/ 7284/7285 depth expansion block 3208 drw 17 q 0 -q 8 d 9 -d n d (n-8) -d n d 18 -d n d (n-8) -d n d 9 -d 17 d 0 -d 8 q 0 -q 8 q 9 -q 17 q 9 -q 17 q (n-8) -q n q (n-8) -q n idt 7201a r a ef a hf a w a ff a w b ff b side 1 side 2 q a0-8 d b0-8 q b0-8 r b hf b ef b idt 7280 7281 7282 7283 7284 7285 d a0-8 fifo b 3208 drw 18 fifo a w data r t rpe in ef data out t wlz t wef t a t ref data valid out 3208 drw 19
11 2975 stender way 800-345-7015 santa clara, ca 95054 fax: 408-492-8674 www.idt.com the idt logo is a registered trademark of integrated device technology, inc. figure 18. write data flow-through mode ordering information note: 1. industrial temperature grade is available by special order for speed grades faster than 20ns. r data w in ff data out t ds t dh t a t wff t rff t wpf data in valid data out valid 3208 drw 20 idt xxxx device type xxx speed x power x package x process/ temperature range blank i 7280 7281 7282 7283 7284 7285 12 15 20 commercial (0 o c to +70 o c) industrial (-40 o c to +85 o c) 256 x 9 dual fifo 512 x 9 dual fifo 1,024 x 9 dual fifo 2,048 x 9 dual fifo 4,096 x 9 dual fifo 8,192 x 9 dual fifo l low power pa thin shrink soic (tssop, so56-2) access time (t a ) speed in nanoseconds 3208 drw 21 (1) commercial commercial commercial and industrial

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